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| ? 2008 microchip technology inc. preliminary ds22067d-page 1 11aa010/11lc010 11aa080/11lc080 11aa020/11lc020 11aa160/11lc160 11aa040/11lc040 features: ? single i/o, uni/o ? serial interface bus ? low-power cmos technology - 1 ma active current, typical - 1 a standby current (max.) (i-temp) ? 128 x 8 through 2,048 x 8 bit organizations ? schmitt trigger inputs for noise suppression ? output slope control to eliminate ground bounce ? 100 kbps max. bit rate ? equivalent to 100 khz clock frequency ? self-timed write cycle (including auto-erase) ? page-write buffer for up to 16 bytes ? status register for added control: - write enable latch bit - write-in-progress bit ? block write protection - protect none, 1/4, 1/2 or all of array ? built-in write protection - power-on/off data protection circuitry - write enable latch ? high reliability - endurance: 1,000,000 erase/write cycles - data retention: > 200 years - esd protection: > 4,000v ? 3-lead sot-23 package ? 8-lead pdip, soic, msop, tdfn packages ? pb-free and rohs compliant ? available temperature ranges: pin function table description: the microchip technology inc. 11aaxxx/11lcxxx (11xx * ) devices are a family of 1 kbit through 16 kbit serial electrically erasable proms. the devices are organized in blocks of x8-bit memory and support the single i/o uni/o? serial bus. by using manchester encoding techniques, the clock and data are combined into a single, serial bit stream (scio), where the clock signal is extracted by the receiver to correctly decode the timing and value of each bit. low-voltage design permits operation down to 1.8v (for 11aaxxx devices), with standby and active currents of only 1 ua and 1 ma, respectively. the 11xx family is available in standard packages including 8-lead pdip and soic, and advanced packaging including 3-lead sot-23, 8-lead tdfn, and 8-lead msop. package types (not to scale) - industrial (i): -40c to +85c - automotive (e): -40c to +125c name function scio serial clock, data input/output v ss ground v cc supply voltage nc nc nc v ss 1 2 3 4 8 7 6 5 v cc nc nc scio pdip/soic (p, sn) nc nc nc v ss 1 2 3 4 8 7 6 5 v cc nc nc scio (ms) tdfn nc nc nc v ss nc nc scio 5 6 7 8 4 3 2 1 v cc (mn) msop sot23 2 3 1 scio v cc v ss (tt) 1k-16k uni/o ? serial eeprom family data sheet * 11xx is used in this document as a generic part number for the 11 series devices.
11aaxxx/11lcxxx ds22067d-page 2 preliminary ? 2008 microchip technology inc. device selection table part number density (bits) organization v cc range page size (bytes) temp. ranges packages 11lc010 1k 128 x 8 2.5-5.5v 16 i,e p, sn, ms, mn, tt 11aa010 1k 128 x 8 1.8-5.5v 16 i p, sn, ms, mn, tt 11lc020 2k 256 x 8 2.5-5.5v 16 i,e p, sn, ms, mn, tt 11aa020 2k 256 x 8 1.8-5.5v 16 i p, sn, ms, mn, tt 11lc040 4k 512 x 8 2.5-5.5v 16 i,e p, sn, ms, mn, tt 11aa040 4k 512 x 8 1.8-5.5v 16 i p, sn, ms, mn, tt 11lc080 8k 1,024 x 8 2.5-5.5v 16 i,e p, sn, ms, mn, tt 11aa080 8k 1,024 x 8 1.8-5.5v 16 i p, sn, ms, mn, tt 11lc160 16k 2,048 x 8 2.5-5.5v 16 i,e p, sn, ms, mn, tt 11aa160 16k 2,048 x 8 1.8-5.5v 16 i p, sn, ms, mn, tt ? 2008 microchip technology inc. preliminary ds22067d-page 3 11aaxxx/11lcxxx 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v scio w.r.t. v ss ............................................................................................................................... ......-0.6v to v cc +1.0v storage temperature ............................................................................................................ ..................... -65c to 150c ambient temperature under bias................................................................................................. .............. -40c to 125c esd protection on all pins..................................................................................................... ..................................... 4 kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability. dc characteristics electrical characteristics: industrial (i): v cc = 2.5v to 5.5v t a = -40c to +85c v cc = 1.8v to 2.5v t a = -20c to +85c automotive (e): v cc = 2.5v to 5.5v t a = -40c to +125c param. no. sym. characteristic min. max. units test conditions d1 v ih high-level input voltage 0.7*v cc v cc +1 v d2 v il low-level input voltage -0.3 -0.3 0.3*v cc 0.2*v cc v v v cc 2.5v v cc < 2.5v d3 v hys hysteresis of schmitt trigger inputs (scio) 0.05*vcc ? v v cc 2.5v (note 1) d4 v oh high-level output voltage v cc -0.5 v cc -0.5 ? ? v v i oh = -300 a, v cc = 5.5v i oh = -200 a, vcc = 2.5v d5 v ol low-level output voltage ? ? 0.4 0.4 v v i o i = 300 a, v cc = 5.5v i o i = 200 a, vcc = 2.5v d6 i o output current limit (note 2) ? ? 4 3 ma ma v cc = 5.5v (note 1) vcc = 2.5v (note 1) d7 i li input leakage current (scio) ?1 av in = v ss or v cc d8 c int internal capacitance (all inputs and outputs) ?7pft a = 25c, f clk = 1 mhz, v cc = 5.0v (note 1) d9 i cc read read operating current ? ? 3 1 ma ma v cc =5.5v; f bus =100 khz, c b =100 pf v cc =2.5v; f bus =100 khz, c b =100 pf d10 i cc write write operating current ? ? 5 3 ma ma v cc = 5.5v v cc = 2.5v d11 iccs standby current ? ? 5 1 a a v cc = 5.5v t a = 125c v cc = 5.5v t a = 85c d12 i cci idle mode current ? 50 av cc = 5.5v note 1: this parameter is periodically sampled and not 100% tested. 2: the scio output driver impedance will vary to ensure i o is not exceeded. 11aaxxx/11lcxxx ds22067d-page 4 preliminary ? 2008 microchip technology inc. table 1-3: ac test conditions table 1-2: ac characteristics ac characteristics electrical characteristics: industrial (i): v cc = 2.5v to 5.5v t a = -40c to +85c v cc = 1.8v to 2.5v t a = -20c to +85c automotive (e): v cc = 2.5v to 5.5v t a = -40c to +125c param. no. sym. characteristic min. max. units test conditions 1f bus serial bus frequency 10 100 khz ? 2t e bit period 10 100 s ? 3t ijit input edge jitter tolerance ? 0.10 ui (note 3) 4f drift serial bus frequency drift rate tolerance ? 0.75 % per byte ? 5f dev serial bus frequency drift limit ?6% per command ? 6t ojit output edge jitter ? 0.25 ui (note 3) 7t r scio input rise time (note 1) ? 100 ns ? 8t f scio input fall time (note 1) ? 100 ns ? 9t stby standby pulse time 600 ? s ? 10 t ss start header setup time 10 ? s ? 11 t hdr start header low pulse time 5?s? 12 t sp input filter spike suppression (scio) ?50ns (note 1) 13 t wc write cycle time (byte or page) ? ? 5 10 ms ms write, wrsr commands eral, setal commands 14 ? endurance (per page) 1m ? cycles 25c, v cc = 5.5v (note 2) note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance ? model which can be obtained on microchip?s web site: www.microchip.com. 3: a unit interval (ui) is equal to 1-bit period (t e ) at the current bus frequency. ac waveform: v lo = 0.2v v hi = v cc - 0.2v c l = 100 pf timing measurement reference level input 0.5 v cc output 0.5 v cc ? 2008 microchip technology inc. preliminary ds22067d-page 5 11aaxxx/11lcxxx figure 1-1: bus timing ? start header figure 1-2: bus timing ? data figure 1-3: bus timing ? standby pulse figure 1-4: bus timing ? jitter scio 2 data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? mak bit nosak bit 11 10 2 scio 7 8 data ? 0 ? data ? 1 ? data ? 1 ? data ? 0 ? 12 scio 9 standby mode ideal edge 3 2 3 6 6 2 6 6 ideal edge ideal edge ideal edge from master from master from slave from slave 11aaxxx/11lcxxx ds22067d-page 6 preliminary ? 2008 microchip technology inc. 2.0 functional description 2.1 principles of operation the 11xx family of serial eeproms support the uni/o ? protocol. they can be interfaced with micro- controllers, including microchip?s pic ? microcon- trollers, asics, or any other device with an available discrete i/o line that can be configured properly to match the uni/o protocol. the 11xx devices contain an 8-bit instruction register. the devices are accessed via the scio pin. table 4-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data is embedded into the i/o stream through man- chester encoding. the bus is controlled by a master device which determines the clock period, controls the bus access and initiates all operations, while the 11xx works as slave. both master and slave can operate as transmitter or receiver, but the master device deter- mines which mode is active. figure 2-1: block diagram scio status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic vcc vss current- limited slope control ? 2008 microchip technology inc. preliminary ds22067d-page 7 11aaxxx/11lcxxx 3.0 bus characteristics 3.1 standby pulse when the master has control of scio, a standby pulse can be generated by holding scio high for t stby . at this time, the 11xx will reset and return to standby mode. subsequently, a high-to-low transition on scio (the first low pulse of the header) will return the device to the active state. once a command is terminated satisfactorily (i.e., via a nomak/sak combination during the acknowledge sequence), performing a standby pulse is not required to begin a new command as long as the device to be selected is the same device selected during the previ- ous command. however, a period of t ss must be observed after the end of the command and before the beginning of the start header. after t ss , the start header (including t hdr low pulse) can be transmitted in order to begin the new command. if a command is terminated in any manner other than a nomak/sak combination, then the master must per- form a standby pulse before beginning a new com- mand, regardless of which device is to be selected. an example of two consecutive commands is shown in figure 3-1. note that the device address is the same for both commands, indicating that the same device is being selected both times. a standby pulse cannot be generated while the slave has control of scio. in this situation, the master must wait for the slave to finish transmitting and to release scio before the pulse can be generated. if, at any point during a command, an error is detected by the master, a standby pulse should be generated and the command should be performed again. figure 3-1: consecut ive commands example 3.2 start data transfer all operations must be preceded by a start header. the start header consists of holding scio low for a period of t hdr , followed by transmitting an 8-bit ? 01010101 ? code. this code is used to synchronize the slave?s internal clock period with the master?s clock period, so accurate timing is very important. when a standby pulse is not required (i.e., between successive commands to the same device), a period of t ss must be observed after the end of the command and before the beginning of the start header. figure 3-2 shows the waveform for the start header, including the required acknowledge sequence at the end of the byte. figure 3-2: start header note: after a por/bor event occurs, a low- to-high transition on scio must be gen- erated before proceeding with communi- cation, including a standby pulse. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak nosak sak standby pulse (1) 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak nosak sak nomak sak t ss note 1: after a por/bor event, a low-to-high transition on scio is required to occur before the first standby pulse. scio data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? data ? 0 ? data ? 1 ? mak nosak t ss t hdr 11aaxxx/11lcxxx ds22067d-page 8 preliminary ? 2008 microchip technology inc. 3.3 acknowledge an acknowledge routine occurs after each byte is transmitted, including the start header. this routine consists of two bits. the first bit is transmitted by the master, and the second bit is transmitted by the slave. the master acknowledge, or mak, is signified by trans- mitting a ? 1 ?, and informs the slave that the current operation is to be continued. conversely, a not acknowledge, or nomak, is signified by transmitting a ? 0 ?, and is used to end the current operation (and initiate the write cycle for write operations). the slave acknowledge, or sak, is also signified by transmitting a ? 1 ?, and confirms proper communication. however, unlike the nomak, the nosak is signified by the lack of a middle edge during the bit period. a nosak will occur for the following events: ? following the start header ? following the device address, if no slave on the bus matches the transmitted address ? following the command byte, if the command is invalid, including read, crrd, write, wrsr, setal, and eral during a write cycle. ? if the slave becomes out of sync with the master ? if a command is terminated prematurely by using a nomak, with the exception of immediately after the device address. see figure 3.3 and figure 3-4 for details. if a nosak is received from the slave after any byte (except the start header), an error has occurred. the master should then perform a standby pulse and begin the desired command again. figure 3-3: acknowledge routine figure 3-4: acknowledge bits 3.4 device addressing a device address byte is the first byte received from the master device following the start header. the device address byte consists of a four bit family code, for the 11xx this is set as ? 1010 ?. the last four bits of the device address byte are the device code, which is hardwired to ? 0000 ?. figure 3-5: device address byte allocation 3.5 bus conflict protection to help guard against high current conditions arising from bus conflicts, the 11xx features a current-limited output driver. the i ol and i oh specifications describe the maximum current that can be sunk or sourced, respectively, by the scio pin. the 11xx will vary the output driver impedance to ensure that the maximum current level is not exceeded. note: a mak must always be transmitted following the start header. note: when a nomak is used to end a write or wrsr instruction, the write cycle is not initiated if no bytes of data have been received. note: in order to guard against bus contention, a nosak will occur after the start header. master slave mak sak mak (? 1 ?) nomak (? 0 ?) sak (? 1 ?) nosak 1 note 1: valid sak. a nosak is defined as any sequence that is not a 1010 000 mak slave address 0 sak ? 2008 microchip technology inc. preliminary ds22067d-page 9 11aaxxx/11lcxxx 3.6 device standby the 11xx features a low-power standby mode during which the device is waiting to begin a new command. a high-to-low transition on scio will exit low-power mode and prepare the device for receiving the start header. standby mode will be entered upon the following conditions: ? a nomak followed by a sak (i.e., valid termina- tion of a command) ? reception of a standby pulse 3.7 device idle the 11xx features an idle mode during which all serial data is ignored until a standby pulse occurs. idle mode will be entered upon the following conditions: ? invalid device address ? invalid command byte, including read, crrd, write, wrsr, setal, and eral during a write cycle. ? missed edge transition ? reception of a mak following a wren , wrdi , setal , or eral command byte ? reception of a mak following the data byte of a wrsr command an invalid start header will indirectly cause the device to enter idle mode. whether or not the start header is invalid cannot be detected by the slave, but will prevent the slave from synchronizing properly with the master. if the slave is not synchronized with the master, an edge transition will be missed, thus causing the device to enter idle mode. 3.8 synchronization at the beginning of every command, the 11xx utilizes the start header to determine the master?s bus clock period. this period is then used as a reference for all subsequent communication within that command. the 11xx features re-synchronization circuitry which will monitor the position of the middle data edge during each mak bit and subsequently adjust the internal time reference in order to remain synchronized with the master. there are two variables which can cause the 11xx to lose synchronization. the first is frequency drift, defined as a change in the bit period, t e . the second is edge jitter, which is a single occurrence change in the position of an edge within a bit period, while the bit period itself remains constant. 3.8.1 frequency drift within a system, there is a possibility that frequencies can drift due to changes in voltage, temperature, etc. the re-synchronization circuitry provides some toler- ance for such frequency drift. the tolerance range is specified by two parameters, f drift and f dev . f drift specifies the maximum tolerable change in bus fre- quency per byte. f dev specifies the overall limit in fre- quency deviation within an operation (i.e., from the end of the start header until communication is terminated for that operation). the start header at the beginning of the next operation will reset the re-synchronization cir- cuitry and allow for another f dev amount of frequency drift. 3.8.2 edge jitter ensuring that edge transitions from the master always occur exactly in the middle or end of the bit period is not always possible. therefore, the re-synchronization cir- cuitry is designed to provide some tolerance for edge jitter. the 11xx adjusts its phase every mak bit, so t ijit specifies the maximum allowable peak-to-peak jitter relative to the previous mak bit. since the position of the previous mak bit would be difficult to measure by the master, the minimum and maximum jitter values for a system should be considered the worst-case. these values will be based on the execution time for different branch paths in software, jitter due to thermal noise, etc. the difference between the minimum and maximum values, as a percentage of the bit period, should be cal- culated and then compared against t ijit to determine jitter compliance. note: in the case of the write , wrsr , setal , or eral commands, the write cycle is initiated upon receipt of the nomak, assuming all other write requirements have been met. note: because the 11xx only re-synchronizes during the mak bit, the overall ability to remain synchronized depends on a combi- nation of frequency drift and edge jitter (i.e., if the mak bit edge is experiencing the max- imum allowable edge jitter, then there is no room for frequency drift). conversely, if the frequency has drifted to the maximum amount tolerable within a byte, then no edge jitter can be present. 11aaxxx/11lcxxx ds22067d-page 10 preliminary ? 2008 microchip technology inc. 4.0 device commands after the device address byte, a command byte must be sent by the master to indicate the type of operation to be performed. the code for each instruction is listed in table 4-1. table 4-1: instruction set 4.1 read instruction the read command allows the master to access any memory location in a random manner. after the read instruction has been sent to the slave, the two bytes of the word address are transmitted, with an acknowl- edge sequence being performed after each byte. then, the slave sends the first data byte to the master. if more data is to be read, the master sends a mak, indicating that the slave should output the next data byte. this continues until the master sends a nomak, which ends the operation. to provide sequential reads in this manner, the 11xx contains an internal address pointer which is incre- mented by one after the transmission of each byte. this address pointer allows the entire memory contents to be serially read during one operation. when the highest address is reached, the address pointer rolls over to address ?0x000? if the master chooses to continue the operation by providing a mak. figure 4-1: read command sequence instruction name instruction code hex code description read 0000 0011 0x03 read data from memory array beginning at specified address crrd 0000 0110 0x06 read data from current location in memory array write 0110 1100 0x6c write data to memory array beginning at specified address wren 1001 0110 0x96 set the write enable latch (enable write operations) wrdi 1001 0001 0x91 reset the write enable latch (disable write operations) rdsr 0000 0101 0x05 read status register wrsr 0110 1110 0x6e write status register eral 0110 1101 0x6d write ? 0x00 ? to entire array setal 0110 0111 0x67 write ? 0xff ? to entire array 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak nomak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 01 0 0 0 0 01 mak nosak sak standby pulse scio sak 15 14 13 12 word address msb 11 10 9 8 mak sak 765 4 word address lsb 321 0 mak sak sak sak sak ? 2008 microchip technology inc. preliminary ds22067d-page 11 11aaxxx/11lcxxx 4.2 current address read ( crrd) instruction the internal address counter featured on the 11xx maintains the address of the last memory array loca- tion accessed. the crrd instruction allows the mas- ter to read data back beginning from this current location. consequently, no word address is provided upon issuing this command. note that, except for the initial word address, the read and crrd instructions are identical, including the ability to continue requesting data through the use of maks in order to sequentially read from the array. as with the read instruction, the crrd instruction is terminated by transmitting a nomak. table 4-2 lists the events upon which the internal address counter is modified. table 4-2: internal address counter figure 4-2: crrd command sequence command event action ? power-on reset counter is undefined read or write mak edge fol- lowing each address byte counter is updated with newly received value read , write , or crrd mak/nomak edge following each data byte counter is incre- mented by 1 note: if, following each data byte in a read , write , or crrd instruction, neither a mak nor a nomak edge is received (i.e., if a standby pulse occurs instead), the internal address counter will not be incremented. note: during a write command, once the last data byte for a page has been loaded, the internal address pointer will rollover to the beginning of the selected page. 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak nomak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 0 0 0 0 01 mak nosak sak standby pulse scio sak sak sak sak 11aaxxx/11lcxxx ds22067d-page 12 preliminary ? 2008 microchip technology inc. 4.3 write instruction prior to any attempt to write data to the 11xx, the write enable latch must be set by issuing the wren instruction (see section 4.4). once the write enable latch is set, the user may pro- ceed with issuing a write instruction (including the header and device address bytes) followed by the msb and lsb of the word address. once the last acknowl- edge sequence has been performed, the master transmits the data byte to be written. the 11xx features a 16-byte page buffer, meaning that up to 16 bytes can be written at one time. to utilize this feature, the master can transmit up to 16 data bytes to the 11xx, which are temporarily stored in the page buf- fer. after each data byte, the master sends a mak, indi- cating whether or not another data byte is to follow. a nomak indicates that no more data is to follow, and as such will initiate the internal write cycle. upon receipt of each word, the four lower-order address pointer bits are internally incremented by one. the higher-order bits of the word address remain con- stant. if the master should transmit data past the end of the page, the address counter will roll over to the begin- ning of the page, where further received data will be written. figure 4-3: write command sequence note: if a nomak is generated before any data has been provided, or if a standby pulse occurs before the nomak is generated, the 11xx will be reset, and the write cycle will not be initiated. note: page write operations are limited to writ- ing bytes within a single physical page, regardless of the number of bytes actu- ally being written. physical page bound- aries start at addresses that are integer multiples of the page size (16 bytes) and end at addresses that are integer multi- ples of the page size minus 1. as an example, the page that begins at address 0x30 ends at address 0x3f. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (over- writing data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page bound- ary. 765 4 data byte 1 321 0 765 4 data byte 2 321 0 765 4 data byte n 321 0 scio mak mak no mak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 1 0 1 1 00 mak nosak sak standby pulse scio sak 15 14 13 12 word address msb 11 10 9 8 mak sak 765 4 word address lsb 321 0 mak sak sak sak sak twc ? 2008 microchip technology inc. preliminary ds22067d-page 13 11aaxxx/11lcxxx 4.4 write enable ( wren ) and write disable ( wrdi ) instructions the 11xx contains a write enable latch. see table 6-1 for the write-protect functionality matrix. this latch must be set before any write operation will be com- pleted internally. the wren instruction will set the latch, and the wrdi instruction will reset the latch. the following is a list of conditions under which the write enable latch will be reset: ? power-up ? wrdi instruction successfully executed ? wrsr instruction successfully executed ? write instruction successfully executed ? eral instruction successfully executed ? setal instruction successfully executed figure 4-4: write enable command sequence figure 4-5: write disable command sequence note: the wren and wrdi instructions must be terminated with a nomak following the command byte. if a nomak is not received at this point, the command will be considered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 0 1 0 0 11 nomak nosak sak standby pulse scio sak 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 01 0 1 0 0 10 nomak nosak sak standby pulse scio sak 11aaxxx/11lcxxx ds22067d-page 14 preliminary ? 2008 microchip technology inc. 4.5 read status register ( rdsr ) instruction the rdsr instruction provides access to the status register. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: the write-in-process (wip) bit indicates whether the 11xx is busy with a write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch. when set to a ? 1 ?, the latch allows writes to the array, when set to a ? 0 ?, the latch prohibits writes to the array. this bit is set and cleared using the wren and wrdi instructions, respectively. this bit is read-only for any other instruction. the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user through the wrsr instruction. these bits are nonvolatile. the wip and wel bits will update dynamically (asyn- chronous to issuing the rdsr instruction). further- more, after the status register data is received, the master can provide a mak during the acknowledge sequence to request that the data be transmitted again. this allows the master to continuously monitor the wip and wel bits without the need to issue another full command. once the master is finished, it provides a nomak to end the operation. figure 4-6: read status register command sequence 7654 3 2 1 0 xxxx bp1 bp0 wel wip note: bits 4-7 are don?t cares, and will read as ? 0 ?. note: if read status register command is initiated while the 11xx is currently executing an internal write cycle on the status register, the new block protection bit values will be read during the entire command. note: the current drawn for a read status register command during a write cycle is a combination of the i cc read and i cc write operating currents. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 0 0 0 0 00 mak nosak sak standby pulse scio sak status register data 321 0 nomak sak the status register data can continuously be read, or polled, by transmitting a mak in place of the nomak. note: 0 0 0 0 ? 2008 microchip technology inc. preliminary ds22067d-page 15 11aaxxx/11lcxxx 4.6 write status register ( wrsr ) instruction the wrsr instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the status register. the array is divided up into four segments. the user has the ability to write-protect none, one, two, or all four of the seg- ments of the array. the partitioning is controlled as illustrated in table 4-3. after transmitting the status register data, the mas- ter must transmit a nomak during the acknowledge sequence in order to initiate the internal write cycle. table 4-3: array protection table 4-4: protected array address locations figure 4-7: write status register command sequence note: the wrsr instruction must be termi- nated with a nomak following the data byte. if a nomak is not received at this point, the command will be considered invalid, and the device will go into idle mode without responding with a sak or executing the command. bp1 bp0 address ranges write-protected address ranges unprotected 00 none all 01 upper 1/4 lower 3/4 10 upper 1/2 lower 1/2 11 all none density upper 1/4 upper 1/2 all sectors 1k 60h-7fh 40h-7fh 00h-7fh 2k c0h-ffh 80h-ffh 00h-ffh 4k 180h-1ffh 100h-1ffh 000h-1ffh 8k 300h-3ffh 200h-3ffh 000h-3ffh 16k 600h-7ffh 400h-7ffh 000h-7ffh 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 10 1 0 1 1 01 mak nosak sak standby pulse scio sak 765 4 status register data 321 0 nomak sak twc 11aaxxx/11lcxxx ds22067d-page 16 preliminary ? 2008 microchip technology inc. 4.7 erase all ( eral ) instruction the eral instruction allows the user to write ?0x00? to the entire memory array with one command. note that the write enable latch (wel) must first be set by issuing the wren instruction. once the write enable latch is set, the user may pro- ceed with issuing a eral instruction (including the header and device address bytes). immediately after the nomak bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ?0x00?. the eral instruction is ignored if either of the block protect bits (bp0, bp1) are not 0, meaning 1/4, 1/2, or all of the array is protected. figure 4-8: erase all command sequence 4.8 set all ( setal ) instruction the setal instruction allows the user to write ?0xff? to the entire memory array with one command. note that the write enable latch (wel) must first be set by issuing the wren instruction. once the write enable latch is set, the user may pro- ceed with issuing a setal instruction (including the header and device address bytes). immediately after the nomak bit has been transmitted by the master, the internal write cycle is initiated, during which time all words of the memory array are written to ?0xff? . the setal instruction is ignored if either of the block protect bits (bp0, bp1) are not 0, meaning 1/4, 1/2, or all of the array is protected. figure 4-9: set all command sequence note: the eral instruction must be termi- nated with a nomak following the com- mand byte. if a nomak is not received at this point, the command will be consid- ered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 1 0 1 1 00 nomak nosak sak standby pulse scio sak twc note: the setal instruction must be termi- nated with a nomak following the com- mand byte. if a nomak is not received at this point, the command will be consid- ered invalid, and the device will go into idle mode without responding with a sak or executing the command. 11 0 1 0 1 00 start header scio device address mak 00 0 0 1 0 10 mak command 11 0 0 1 1 01 nomak nosak sak standby pulse scio sak twc ? 2008 microchip technology inc. preliminary ds22067d-page 17 11aaxxx/11lcxxx 5.0 data protection the following protection has been implemented to prevent inadvertent writes to the array: ? the write enable latch (wel) is reset on power- up ?a write enable ( wren ) instruction must be issued to set the write enable latch ? after a write, eral, setal, or wrsr command, the write enable latch is reset ? commands to access the array or write to the status register are ignored during an internal write cycle and programming is not affected 6.0 power-on state the 11xx powers on in the following state: ? the device is in low-power shutdown mode, requiring a low-to-high transition on scio to enter idle mode ? the write enable latch (wel) is reset ? the internal address pointer is undefined ? a low-to-high transition, standby pulse and subse- quent high-to-low transition on scio (the first low pulse of the header) are required to enter the active state . table 6-1: write protec t functionality matrix wel protected blocks unprotected blocks status register 0 protected protected protected 1 protected writable writable 11aaxxx/11lcxxx ds22067d-page 18 preliminary ? 2008 microchip technology inc. 7.0 pin descriptions the descriptions of the pins are listed in table 7-1. table 7-1: pin function table 7.1 serial clock, data input/output (scio) scio is a bidirectional pin used to transfer commands and addresses into, as well as data into and out of, the device. the serial clock is embedded into the data stream through manchester encoding. each bit is rep- resented by a signal transition at the middle of the bit period. name 3-pin sot-23 8-pin pdip/soic/ msop/tdfn description scio 1 5 serial clock, data input/output v cc 2 8 supply voltage v ss 3 4 ground nc ? 1,2,3,6,7 no internal connection ? 2008 microchip technology inc. preliminary ds22067d-page 19 11aaxxx/11lcxxx 8.0 packaging information 8.1 package marking information t/xxxnnn xxxxxxxx yyww 8-lead pdip i/p 1l7 11aa160 0828 example: 3 e 8-lead pdip package marking (pb-free) device line 1 marking device line 1 marking 11aa010 11aa010 11lc010 11lc010 11aa020 11aa020 11lc020 11lc020 11aa040 11aa040 11lc040 11lc040 11aa080 11aa080 11lc080 11lc080 11aa160 11aa160 11lc160 11lc160 note: t = temperature grade (i, e) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 11aaxxx/11lcxxx ds22067d-page 20 preliminary ? 2008 microchip technology inc. 8-lead soic xxxxyyww xxxxxxxt nnn example: sn 0828 11aa160i 1l7 3 e 8-lead soic package marking (pb-free) device line 1 marking device line 1 marking 11aa010 11aa010t 11lc010 11lc010t 11aa020 11aa020t 11lc020 11lc020t 11aa040 11aa040t 11lc040 11lc040t 11aa080 11aa080t 11lc080 11lc080t 11aa160 11aa160t 11lc160 11lc160t note: t = temperature grade (i, e) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e ? 2008 microchip technology inc. preliminary ds22067d-page 21 11aaxxx/11lcxxx 3 e 8-lead msop (150 mil) example: xxxxxxt ywwnnn 11a01i 8281l7 8-lead msop package marking (pb-free) device line 1 marking device line 1 marking 11aa010 11a01t 11lc010 11l01t 11aa020 11a02t 11lc020 11l02t 11aa040 11a04t 11lc040 11l04t 11aa080 11a08t 11lc080 11l08t 11aa160 11aat 11lc160 11lat note: t = temperature grade (i, e) legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 11aaxxx/11lcxxx ds22067d-page 22 preliminary ? 2008 microchip technology inc. 8-lead 2x3 tdfn example : xxx yww nn d51 828 17 8-lead 2x3 tdfn package marking (pb-free) device i-temp marking device i-temp marking e-temp marking 11aa010 d11 11lc010 d14 d15 11aa020 d21 11lc020 d24 d25 11aa040 d31 11lc040 d34 d35 11aa080 d41 11lc080 d44 d45 11aa160 d51 11lc160 d54 d55 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e ? 2008 microchip technology inc. preliminary ds22067d-page 23 11aaxxx/11lcxxx 3-lead sot-23 xxnn example: b517 3-lead sot-23 package marking (pb-free) device i-temp marking device i-temp marking e-temp marking 11aa010 b1nn 11lc010 m1nn n1nn 11aa020 b2nn 11lc020 m2nn n2nn 11aa040 b3nn 11lc040 m3nn n3nn 11aa080 b4nn 11lc080 m4nn n4nn 11aa160 b5nn 11lc160 m5nn n5nn legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 11aaxxx/11lcxxx ds22067d-page 24 preliminary ? 2008 microchip technology inc. !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# / !# '! #& .0 1,21 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 7,8. '! 9'&! 7 7: ; 7"') % ! 7 < & 1, & & = = ## 4 4!! - 1 !& & = = "# & "# >#& . - - ## 4 >#& . < : 9& -< -? & & 9 - 9 # 4!! < 6 9 #>#& ) ? 9 * 9 #>#& ) < : * + 1 = = - n e1 note 1 d 12 3 a a1 a2 l b1 b e e eb c * , <1 ? 2008 microchip technology inc. preliminary ds22067d-page 25 11aaxxx/11lcxxx ! ""#$%& !' !" #$% &" ' ()"&'"!&) &#*& & & # +% &, & !& - '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & 1, : 8 & = = ## 4 4!! = = & # %% + = : >#& . ?1, ## 4 >#& . -1, : 9& 1, , '% @ & a = 3 &9& 9 = 3 & & 9 .3 3 & b = #& ) - = # %& b = b # %&1 && ' b = b d n e e e1 note 1 12 3 b a a1 a2 l l1 c h h * , 1 11aaxxx/11lcxxx ds22067d-page 26 preliminary ? 2008 microchip technology inc. ! ""#$%& !' 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. preliminary ds22067d-page 27 11aaxxx/11lcxxx ( " ! )*( ( ! !" #$% &" ' ()"&'"!&) &#*& & & # '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# - '! #& .0 1,2 1 !'! & $ & "! **& "&& ! .32 % '! ("!" *& "&& (% % ' & " !! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 < & ? 1, : 8 & = = ## 4 4!! < & # %% = : >#& . 1, ## 4 >#& . -1, : 9& -1, 3 &9& 9 ? < 3 & & 9 .3 3 & b = #& ) = d n e e1 note 1 1 2 e b a a1 a2 c l1 l * , 1 11aaxxx/11lcxxx ds22067d-page 28 preliminary ? 2008 microchip technology inc. + $ )*( ,--%./ 0+ 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 ? 2008 microchip technology inc. preliminary ds22067d-page 29 11aaxxx/11lcxxx + $ )*( ,--%./ 0+ 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 11aaxxx/11lcxxx ds22067d-page 30 preliminary ? 2008 microchip technology inc. ! 0" "00 !0, '! ! #. # &"#' #% ! & "! ! #% ! & "! !! &$# '' !# '! #& .0 1,2 1 !'! & $ & "! **& "&& ! 3 & ' !&" & 4 # *!( !!& 4 % & &# & && 255***' '5 4 6&! 99. . '! 9'&! 7 7: ; 7"') % ! 7 - 9 # & 1, :"&!#9 # & 1, : 8 & < = ## 4 4!! & # %% = : >#& . = ? ## 4 >#& . ? - : 9& ? - 3 &9& 9 - ? 3 & b = b 9 # 4!! < = 9 #>#& ) - = b n e e1 2 1 e e1 d a a1 a2 c l * , 1 ? 2008 microchip technology inc. preliminary ds22067d-page 31 11aaxxx/11lcxxx appendix a: revision history revision a (10/07) original release of this document. revision b (01/08) revised sot-23 package type; revised dfn package to tdfn; section 3.3 (added new bullet item); section 4.5 note; table 7-1. revision c (03/08) removed patent pending notice; revised tables 1-1 and 1-2; section 3.3 (bullet 3) and 3.7 (bullet 2); product id system. revision d (04/08) revised document status to preliminary; general updates. 11aaxxx/11lcxxx ds22067d-page 32 preliminary ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. preliminary ds22067d-page 33 11aaxxx/11lcxxx the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com 11aaxxx/11lcxxx ds22067d-page 34 preliminary ? 2008 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22067d 11aaxxx/11lcxxx 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2008 microchip technology inc. preliminary ds22067d-page 35 11aaxxx/11lcxxx product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x x /xx x package temperature tape & reel device device: 11aa010 1 kbit, 1.8v uni/o serial eeprom 11lc010 1 kbit, 2.5v uni/o serial eeprom 11aa020 2 kbit, 1.8v uni/o serial eeprom 11lc020 2 kbit, 2.5v uni/o serial eeprom 11aa040 4 kbit, 1.8v uni/o serial eeprom 11lc040 4 kbit, 2.5v uni/o serial eeprom 11aa080 8 kbit, 1.8v uni/o serial eeprom 11lc080 8 kbit, 2.5v uni/o serial eeprom 11aa160 16 kbit, 1.8v uni/o serial eeprom 11lc160 16 kbit, 2.5v uni/o serial eeprom tape & reel: t = tape and reel blank = tube temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: p = 8-lead plastic dip (300 mil body) sn = 8-lead plastic soic (3.90 mm body) ms = 8-lead plastic micro small outline (msop) mny (1) = 8-lead 2x3 mm tdfn tt = 3-lead sot 23 (tape and reel only) examples: a) 11aa010-i/p = 1 kbit, 1.8v serial eeprom, industrial temp., pdip package b) 11lc160t-e/tt = 16 kbit, 2.5v serial eeprom, extended temp., tape & reel, sot-23 package c) 11aa080-i/ms = 8 kbit, 1.8v serial eeprom, industrial temp., msop package d) 11lc020t-i/sn = 2 kbit, 2.5v serial eeprom, industrial temp., tape & reel, soic package e) 11aa040t-i/mny = 4 kbit, 1.8v serial eeprom, industrial temp., tape and reel, 2x3 mm tdfn package, nickel palladium gold finish range note 1: ?y? indicates a nickel palladium gold (nipdau) finish. 11aaxxx/11lcxxx ds22067d-page 36 preliminary ? 2008 microchip technology inc. notes: ? 2008 microchip technology inc. preliminary ds22067d-page 37 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pro mate, rfpic and smartshunt are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. filterlab, linear active thermistor, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, appl ication maestro, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, in-circuit serial programming, icsp, icepic, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, pickit, picdem, picdem.net, pictail, pic 32 logo, powercal, powerinfo, powermate, powertool, real ice, rflab, select mode, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2008, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ds22067d-page 38 preliminary ? 2008 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 santa clara santa clara, ca tel: 408-961-6444 fax: 408-961-6445 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2401-1200 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 01/02/08 |
Price & Availability of 11LC160-EMNY
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